This application claims priority under 35 USC § 119 to Korean Patent Application No. 2003-0063579 and Korean Patent Application No. 2004-0000228, filed on Sep. 15, 2003 and Jan. 5, 2004 respectively, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates generally to a capacitance multiplier, and more particularly to a capacitance multiplier having self-biasing, cascode loads, and/or a plurality of multiplying paths, for higher efficiency in generating the multiplied capacitance.
2. Description of the Related Art
A capacitance multiplier is a circuit that multiplies a capacitance of a capacitor. FIG. 1A is a circuit diagram illustrating a conventional capacitance multiplier, and FIG. 1B illustrates a small-signal model of the capacitance multiplier of FIG. 1A.
Such a capacitance multiplier is discussed in detail in a document, Sergio Solis-Bustos, Jose Silva-Martinez, Franco Maloberti, and Edgar Sanchez-Sinencio, “A 60-dB Dynamic-Range CMOS Sixth-Order 2.4-Hz Low-Pass Filter for Medical Applications”, IEEE Transactions on Circuits and Systems II, vol. 47, no. 12, Dec. 2000.
Referring to FIG. 1A, a level of current flowing through a first PMOS transistor MP1 influences operation of a second PMOS transistor MP2. Operation of the first PMOS transistor MP1 is influenced by a level of a bias current IBIAS which also then influences operation of the second PMOS transistor MP2.
On the other hand, a level of current flowing through the first NMOS transistor MN1 influences operation of a second NMOS transistor MN2. Thus, operations of the PMOS and NMOS transistor MP2 and MN2 are influenced by levels of different bias currents. As a result, when the PMOS and NMOS transistors MP2 and MN2 are mismatched, the capacitance multiplier of FIG. 1A may not operate with stability.
Referring to FIG. 1B, by small-signal analysis, a total current flowing in a first node is expressed as follows:
            i      in        =                  (                  1          +          N                )            ×                        S          ×                      C            i                                    1          +                      s            ×                                          C                i                                            g                mn1                                                        ×              V        in              ,where iin and vin are a current and a voltage, respectively, at the first node. gmn1 is the transconductance of the first NMOS transistor MN1 when leakage currents flowing through the PMOS and NMOS transistors MP2 and MN2 are negligible.
N is a size multiplication ratio between the PMOS transistors MP1 and MP2, and between the NMOS transistors MN1 and MN2. Thus, the W/L (width to length ratio) of the second PMOS transistor MP2 is N times the W/L of the first PMOS transistor MP1. Similarly, the W/L of the second NMOS transistor MN2 is N times the W/L of the first NMOS transistor MN1.
Here, a bandwidth of the capacitance multiplier of FIGS. 1A and 1B is expressed as follows: w=gmn1/Ci. In this manner, an output capacitance of Ci*(N+1) within the above bandwidth is generated at the first node.
Unfortunately, the capacitance multiplier of FIGS. 1A and 1B has a relatively narrow bandwidth and requires a relatively high area for a bias circuit comprised of the current source for IBIAS and the extra MOS transistors MP3, MN3, and MN4. As a result, when the prior art capacitance multiplier is integrated into an application system such as a frequency synthesizer, a chip size of the application system is greatly increased. Hence, it is desired to increase a bandwidth of a capacitance multiplier but also with a reduced area.